The present invention relates to a method of manufacturing a semiconductor device and more particularly to a technique which is effective in its application to a technique (MAP: Matrix Array Packaging method) of manufacturing plural semiconductor devices. According to this technique, a main surface side of a substrate with plural semiconductor chips (semiconductor elements) arranged thereon regularly in longitudinal and transverse directions is covered with a seal member (package) by block molding of an insulating resin and thereafter the substrate and the package superimposed one on the other are divided longitudinally and transversely to fabricate plural semiconductor devices.
As package forms of semiconductor devices adapted for the tendency to multi-function and higher density there are known, for example, BGA (Ball Grid Array) and CSP (Chip Size Package). As an example of a technique for fabricating such BGA and CSP there is known a semiconductor device manufacturing method comprising providing a wiring substrate, mounting a semiconductor chip (semiconductor element) at a predetermined position of a main surface of the wiring substrate, connecting electrodes on the semiconductor chip and wiring lines on the main surface of the wiring substrate with each other through electrically conductive wires, then covering the main surface side of the wiring substrate with an insulating sealing resin, and forming salient electrodes (bump electrodes) on a back surface of the wiring substrate, the salient electrodes being connected to the wiring lines.
For the purpose of reducing the semiconductor device manufacturing cost there has been adopted an MAP method comprising using a matrix type wiring substrate with product forming areas provided longitudinally and transversely in a lattice shape, mounting predetermined semiconductor chips in the product forming areas, respectively, of the matrix wiring substrate, thereafter connecting electrodes of the semiconductor chips and wiring lines on a main surface of the wiring substrate with each other through electrically conductive wires, then covering the whole of the main surface side of the matrix wiring substrate with an insulating sealing resin (block molding), forming salient electrodes (bump electrodes) on a back surface of the wiring substrate, the salient electrodes being connected to the wiring lines, and subsequently cutting the matrix wiring substrate and the package of the sealing resin longitudinally and transversely to fabricate plural semiconductor devices.
In the conventional transfer molding, including block molding, a cavity into which resin is injected, as well as gates and air vents both communicating with the cavity, are formed using a molding die.
In block molding, if an air vent is not formed correspondingly on an extension of semiconductor chips arranged in a column, the flow of resin in the cavity changes delicately, resulting in that voids remain on edges of the semiconductor chips which edges are hidden with respect to the resin flow, or unfilling of resin is apt to occur.
FIGS. 22 to 24 are schematic diagrams associated with a block molding method which the present inventor had studied before accomplishing the present invention. As shown in FIG. 22, a substrate 20 with semiconductor chips 10 arranged regularly on a main surface (an upper surface in the figure) thereof is held grippingly (mold clamping) between a lower mold 30B and an upper mold 30A of a molding die 30, whereby there are formed a cavity 31, as well as gates 32 and air vents 37 both communicating with the cavity 31. Generally, a mating surface(s) (parting surface(s)) of the upper mold 30A and/or the lower mold 30B is (are) recessed for forming the cavity 31, gates 32 and air vents 37.
In the MAP method, a molding space (cavity) including all the semiconductor chips 10 fixed to the main surface of the substrate 20 is formed on the main surface side of the substrate. On one side of the cavity 31 are arranged plural gates 32 side by side, the gates 32 serving as flow paths for guiding molten resin 8 into the cavity 31, while on another side (opposite side) opposite to the gates 32 are formed plural air vents 37 side by side, the air vents 37 serving as flow paths for guiding air 9 to the outside of the cavity 31 which air is forced out by the resin 8 flowing into the cavity 31.
FIGS. 23 and 24 are schematic diagrams showing arrangement relations among the cavity 31 formed in the substrate 20, the gates 32 and air vents 37, and the semiconductor chips 10 mounted on the main surface of the substrate 20. In FIGS. 22, 23 and 24, which illustrate arrangement relations of the substrate 20 to the semiconductor chips 10 arranged on the substrate, wires for electrically connecting electrodes on the semiconductor chips 10 with wiring lines on the substrate 20 are not shown.
FIG. 23 shows such a positional relation between semiconductor chips and air vents as permits preventing the occurrence of voids and unfilling of resin. In FIG. 23, semiconductor chips 10 are arranged regularly in a lattice shape along both long and short sides of the substrate 20 which is quadrangular. In the example illustrated in the same figure, a total of twelve semiconductor chips 10 are arranged as three rows and four columns. That is, three semiconductor chips 10 are arranged in each column from gates 32 located on one side of the cavity 31 toward air vents 37 located on another side of the cavity 31 opposite to the gates 32.
The air vents 37 are arranged correspondingly to the columns of semiconductor chips. The area between adjacent semiconductor chip columns, (chip-column-to-chip-column area), is wide as a resin flow path and encounters neither concave nor convex that obstruct the flow of resin, so that the flow velocity of resin flowing between adjacent chip columns becomes higher than that in a chip column area (a combined area of both areas where semiconductor chips are arranged and chip-to-chip areas in the columns of chips arranged in the direction in which the resin is injected). Consequently, the resin arrives so much earlier at a terminal end of the substrate 20 where the air vents 37 are arranged. Therefore, the air vents 37 are deviated from the extension of each chip-column-to-chip-column area and are arranged correspondingly to the extensions of the chip column areas.
FIG. 24 is a schematic diagram showing a substrate 20 as clamped to the molding die 30 illustrated in FIG. 23, the substrate 20 having a different arrangement of semiconductor chips. On a main surface of this substrate 20 are arranged semiconductor chips 10 regularly in seven columns and four rows. Since the air vents 37 are formed by the molding die 30, their positions do not always correspond to positions located on the extensions of chip column areas and air vents located on the extensions of chip-column-to-chip-column areas are stopped up with resin and fail to function the moment the resin reaches the terminal end of the cavity past the chip-column-to-chip-column areas. In the portions where air vents are not provided on the extensions of chip-column-to-chip-column areas, the resin passing between adjacent chip-column-to-chip-column areas involves remaining air therein and generates voids upon arrival at the terminal end of the cavity.
For solving such a problem, that is, for forming air vents correspondingly to chip columns, it is necessary to provide molding dies correspondingly to various substrates, with consequent increase of the mold cost and hence increase in the cost of the semiconductor device manufactured by the MAP method.
It is an object of the present invention to provide a semiconductor device manufacturing method in accordance with an MAP method which can reduce the mold cost.
It is another object of the present invention to provide a semiconductor device manufacturing method in accordance with an MAP method which can reduce the semiconductor device manufacturing cost.
The above and other objects and novel features of the present invention will become apparent from the following description and the accompanying drawings.
Typical inventions disclosed herein will be outlined below.
(1) A semiconductor device manufacturing method comprising the steps of:
providing a substrate, the substrate having product forming areas arranged regularly on a main surface thereof and also having wiring lines of predetermined patterns formed on main surfaces and back surfaces opposite thereto of the product forming areas, the wiring lines on the main surfaces and the wiring lines on the back surfaces being electrically connected with each other through conductors which extend through the substrate from the main surfaces to the back surfaces;
fixing semiconductor chips respectively to the product forming areas on the main surface of the substrate;
connecting electrodes formed on upper surfaces of the semiconductor chips with wiring lines formed on the main surface of the substrate electrically using electrically conductive connecting means;
clamping the substrate between a lower mold and an upper mold of a molding die in transfer molding equipment to form a cavity on the main surface side of the substrate, as well as gates and air vents connected to the cavity, then feeding molten insulating resin into the cavity through the gates and at the same time forcing out air present within the cavity to the exterior of the cavity through the air vents to form a block molding package on the main surface side of the substrate, the block molding package being formed of a single resin and covering the semiconductor chips and the connecting means;
forming salient electrodes on wiring portions on a back surface of the substrate; and
dividing the substrate and the block molding package, which are superimposed one on the other, longitudinally and transversely at predetermined positions to form plural semiconductor devices,
wherein grooves reaching an edge of the substrate are partially formed in a peripheral edge portion of the substrate so that the grooves form the air vents when the substrate is clamped between the lower and upper molds of the molding die.
The wiring on the substrate has plural product forming areas for the production of the semiconductor devices, which product forming areas are arranged regularly. The foregoing grooves are formed on extensions of the chip column areas of semiconductor chips fixed to the product forming areas and not formed on extensions of the chip-column-to-chip-column areas. A material is provided selectively on a surface of a base material which constitutes the substrate and each of the said grooves is formed by a portion free of the said material and portions located on both sides thereof and provided with the same material. The width of each of the grooves is smaller than the width of each semiconductor chip (e.g., about half of the chip width) and the depth thereof is about 50 xcexcm. An inner end of each of the grooves is arranged inside the cavity at a position of about 100 xcexcm to 1 mm from the edge of the cavity. A maximum particle diameter of a filler contained in the sealing resin is larger than the height of the air vents.
According to the above means (1), (a) the air vents can be defined by the grooves formed in the substrate. Therefore, it is no longer required for the molding die to be provided with air vents and hence it is possible to improve the versatility (sharing) of the molding die. As a result, it is possible to attain the reduction of the semiconductor device manufacturing cost.
(b) The grooves can be formed correspondingly to the arrangement of semiconductor chips on the substrate and can be formed on extensions of the chip column areas of semiconductor chips fixed to the product forming areas, not formed on extensions of the chip-column-to-chip-column areas, whereby it becomes possible to let the flow of resin appropriate within the cavity, and voids and unfilling of resin become difficult to occur. Consequently, it becomes possible to form a package of high quality and the semiconductor device manufacturing cost can be reduced.
(c) Since a material is provided selectively on the surface of the base material which constitutes the substrate and each of the foregoing grooves is defined by a portion free of the said material and portions located on both sides thereof and provided with the said material, not only the grooves can be formed accurately and easily, but also the substrate cost can be kept low.
(d) Since the maximum particle diameter of the filler contained in the sealing resin is larger than the height of the air vents, the resin which contains voids can be conducted surely to the outside of the cavity and it is possible to prevent the resin from flowing out more than necessary through the air vents. Thus, not only it is possible to prevent a wasteful consumption of the resin, but also it is possible to increase the resin injection pressure in the transfer molding process and thereby prevent the occurrence of a resin unfilled portion and large voids therein.